The present invention relates to methods and apparatus for processing integrated circuits.
An integrated circuit is typically formed on a substrate by the sequential deposition of conductive, semiconductive or insulative layers on a silicon wafer. One fabrication step involves depositing a filler layer over a non-planar surface, and planarizing the filler layer until the non-planar surface is exposed. For example, a conductive filler layer, such as copper, can be deposited on a patterned insulative layer to fill the trenches or holes in the insulative layer. The filler layer is then polished until the raised pattern of the insulative layer is exposed. After planarization, the portions of the conductive layer remaining between the raised pattern of the insulative layer form vias, plugs and lines that provide conductive paths between thin film circuits on the substrate. In addition, planarization is needed to planarize the substrate surface for photolithography.
Chemical mechanical polishing (CMP) is one accepted method of planarization. This planarization method typically requires that the substrate be mounted on a carrier or polishing head. The exposed surface of the substrate is placed against a rotating polishing disk pad or belt pad. The polishing pad can be either a “standard” pad or a fixed-abrasive pad. A standard pad has a durable roughened surface, whereas a fixed-abrasive pad has abrasive particles held in a containment medium. The carrier head provides a controllable load on the substrate to push it against the polishing pad. A polishing liquid, including at least one chemically reactive agent, is supplied to the surface of the polishing pad. The polishing liquid can optionally include abrasive particles, e.g., if a standard pad is used.
A variation of CMP, which is particularly useful for copper polishing, is electrochemical mechanical processing (ECMP). The ECMP process is similar to the conventional CMP process, but has been designed for copper film polishing at very low down and shear forces, and is therefore suitable for low-k/Cu technologies. In ECMP techniques, conductive material is removed from the substrate surface by electrochemical dissolution while concurrently polishing the substrate, typically with reduced mechanical abrasion as compared to conventional CMP processes. The electrochemical dissolution is performed by applying a bias between a cathode and the substrate surface and thus removing conductive material from the substrate surface into a surrounding electrolyte.
Ideally, the CMP or ECMP process polishes the substrate layer to a desired planarity and thickness. Polishing beyond this point can lead to overpolishing (removing too much) of a conductive layer or film, which can lead to increased circuit resistance. Not polishing the substrate enough, or underpolishing (removing too little) of the conductive layer, can lead to electrical shorting. Variations in the initial thickness of the substrate layer, the polishing solution composition, the polishing pad condition, the relative speed between the polishing pad and the substrate, and the load on the substrate can cause variations in the material removal rate. These variations can occur between substrates or across the radius of a single substrate, such as when a substrate is over polished in one region and underpolished in another region. The CMP or ECMP apparatus can be selected to control the rate of polishing of a substrate.